1. Field of the Invention
The present invention relates generally to the field of semiconductor devices, and more particularly, to a method of planarizing the surface of a semiconductor device and reduce the occurrence of the dishing phenomenon and a semiconductor device manufactured according to the method. The present invention also relates to a method of increasing the removal rate ratio of a medium material layer to an oxide layer during chemical mechanical polishing (CMP).
2. Description of the Related Art
As the density and size of semiconductor devices decrease and the interconnection structure of semiconductor devices are multiplied, the height of the steps on the surfaces of the semiconductor devices have increased. In order to planarize the surface steps, a spin-on glass (SOG) process, an etch back process, or a chemical mechanical polishing (CMP) process is typically used.
When CMP is used as a wide area planarizing technique, a wafer surface is pressed against a polishing pad while an abrasive slurry flows to a contact area of the wafer and the polishing pad. The wafer surface chemically reacts with the slurry, while the polishing pad and the wafer, which rotate relative to each other, physically planarize irregularities on the wafer surface.
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method of separating an active region, where operations of a semiconductor device occur, from a field region, which is an inactive region, by filling a trench with an oxide layer in a shallow trench isolation (STI) process and planarizing the surface of the oxide layer using CMP.
Referring to FIG. 1, an etch stop layer 12 for CMP (e.g., a silicon nitride layer) is formed on a silicon substrate 10. A photolithography process using a photoresist layer (not shown) is then performed so that an etch stop layer pattern is formed which defines a region where trenches will be located. Next, the silicon substrate 10 is etched using the etch stop layer pattern as an etch mask so that a trench region 14 having a desired depth is formed. A silicon oxide layer 16 is blanket-deposited on the silicon substrate 10 and the trench region 14. As a result, the trench region 14 is filled with an oxide layer having an excellent gap-fill characteristic.
Optionally, a pad oxide layer (not shown) may be formed on the substrate 10 before the etch stop layer 12 (e.g., silicon nitride layer) is formed. In another example, a thermal oxide layer (not shown) or a liner layer (not shown) may be formed on the bottom and the sidewalls of the trench region 14 before the silicon oxide layer 16 is deposited in the trench region 14.
Referring to FIG. 2, CMP is performed on the silicon oxide layer 16 to expose the etch stop layer 12. Thereafter, the etch stop layer 12 is removed so that a field region for isolating devices is formed. In the field region, the trench region 14 in the silicon substrate 10 is filled with a silicon oxide layer 16a. 
A plurality of trench regions 14 having various widths can be formed in the silicon substrate 10 depending upon the circuit design. When the width of the trench region 14 is large, a large amount of the silicon oxide layer 16 remains after CMP. As a result, CMP is excessively performed to remove the remaining silicon oxide layer 16. Thus, a large amount of the silicon oxide layer 16 in the trench region 14 (which has a relatively small width) is removed, which results in a dishing phenomenon (e.g., the silicon oxide layer 16 has a concave shape), as is shown in FIG. 2. Because the dishing phenomenon deteriorates the surface planarity of the silicon substrate and causes defects in the semiconductor device, it is desirable to reduce the occurrence of the dishing phenomenon.